1. Field of the Invention
This invention relates generally to a method of manufacturing high performance semiconductor devices and a method of inspecting the high performance semiconductor devices during manufacturing processing. More specifically, this invention relates to a method of predicting yield during processing of the high performance semiconductor devices. Even more specifically, this invention relates to a method of predicting yield during processing of the high performance semiconductor devices using automatic defect classification determined killer ratios, die health statistics and die stacking.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continually increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects occurring during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increase the cost of the remaining usable chips.
Each semiconductor chip requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. In order to etch metal lines, for example, a layer of photoresist is formed on the surface of the semiconductor chips and patterned by developing the photoresist and washing away the unwanted portion of the photoresist. Because the metal lines and other metal structures have xe2x80x9ccriticalxe2x80x9d dimensions, that is, dimensions that can affect the performance of the semiconductor chip, the process of forming the photoresist pattern for each layer is examined during the manufacturing process. Some of these process steps involve placing the wafer in which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
In the course of modern semiconductor manufacturing, semiconductor wafers are routinely inspected using xe2x80x9cscanningxe2x80x9d tools to find defects. A scanning tool determines the location and other information concerning defects that are caught and this information is stored in a data file for later recapture and inspection of any of the defects. These data files are stored in a relational database that has the ability to generate wafer maps with defects shown in their relative positions. The data database typically has the ability to send these wafer map files to various review tools within the manufacturing plant. This is very useful as it allows for re-inspection on various after-scan inspection tools within the manufacturing plant. These inspection tools include Optical Microscopes and Scanning Electron Microscopes (SEMs) that allow for classification of the defects. Images taken on the various after-scan inspection tools can be linked by linkage data to the defect on a wafer map and reviewed at a workstation at the convenience of an engineer or technician.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products a great deal of time, effort and money is expended on the capture and classification of silicon based defects. Once a defect is caught and properly described, work can begin in earnest to resolve the cause of the defect, to attempt elimination of the cause of the defect, and to determine adverse effects of the defect on device parametrics and performance.
In the course of typical semiconductor manufacturing and processing of semiconductor wafers a great deal of effort is increasingly being placed on determining the quality of the wafers from a defect viewpoint. This is commonly measured in terms of defectivity, defined as defects/cm2 or per cent defective die. Additionally, it is becoming increasingly prevalent for semiconductor wafers undergoing a manufacturing process to be inspected at numerous processing steps during a process flow. While defectivity gives an indication of the quality of the wafer at a given inspection, it does not provide the desired information, that is, how many die were killed at this step. In addition, there is no indication of how the defects from previous inspections may affect the wafer at the current inspection, unless the defects were caught in a previous layer (a propagator, which is a defect that is caught on a first layer and a subsequent layer inspection).
In the typical ADC (automatic defect classification) methodology, after a scan tool has captured defects, the defects are recaptured and reviewed on an optical review tool and automatically classified by the methodology of automatic defect classification (ADC). In an ADC methodology, the ADC tools have been programmed to recognize parameters, called descriptors, of a defect, assign values to the parameters and to classify the defect based upon the values assigned to the defect. U.S. Pat. No. 5,862,055, xe2x80x9cADC INDIVIDUAL DEFECT PREDICATE VALUE RETENTION AND USAGE and U.S. patent application, Ser. No. 08/896,341, xe2x80x9cAUTOMATIC DEFECT CLASSIFICATION (ADC) RECLASSIFICATION ENGINExe2x80x9d, both of which are enclosed by reference in their entirety, describe the ADC methodology. The classification information is sent to a relational database, which is part of a defect management system (DMS). The classification information can be retrieved for further processing, analysis, off-line viewing, charting and other analysis procedures. With the advent of ADC and the availability of large databases it would be advantageous to be able to assign a killer or kill ratio to any particular defect. It would be advantageous to tabulate the defect and the associated defect kill ratio on each layer. It would also be advantageous to determine and store a die health statistic for each die at each inspection layer. In addition, it would be of great benefit to have the ability to combine the die health statistics from all the inspections to give a xe2x80x9cstackedxe2x80x9d or overall wafer health statistic.
Therefore, what is needed is a methodology that determines and assigns killer ratios based on ADC classifications, tabulates the defects per layer and the associated defect kill ratio, calculates die health statistics for every die, and determines wafer health statistics for every layer as well as the stacked wafer health statistic for the current layer.
According to the present invention, the foregoing and other objects and advantages are attained by a method of manufacturing high performance semiconductor integrated devices in which defects are captured and a kill ratio is used to analyze the semiconductor process.
In accordance with an aspect of the invention, layers on a manufacturing lot of semiconductor wafers are processed, at least one inspection wafer is inspected for defects in a scan tool which generates defect information. The defects captured by the scan tool are reviewed in an ADC classification tool and the classification information is correlated with kill ratio information by a defect management system.
In accordance with a first embodiment of the invention, the classification (type) of defects and associated kill ratio is tabulated in a defect table.
In accordance with an aspect of the first embodiment of the invention, a defect table is generated for each of the processed and inspected layers.
In accordance with a second embodiment of the invention, the classification (type) of defects and kill ratio are correlated and the die number having the defect and the kill ratio are tabulated in a stacked defect table. A die health statistic is calculated from the kill ratio for each die for each layer. The die health statistics for each layer is carried over to the next defect table and is used to calculate a cumulative die health statistic.
The method of the present invention thus provides a semiconductor manufacturing and inspection process for the manufacture of high performance integrated circuits that provides a first defect table in which defect type and associated kill ratios are tabulated by layer and a second stacked defect table in which the number of dice having defects and a calculated die health statistic are tabulated per layer. A cumulative die health statistic is determined per die and is carried over to the next layer defect table. The tabulated data is utilized to predict yield and analyze the manufacturing process.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.